(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and in particular, to a method of forming a square spacer to alleviate the problem of bridging during the salicide process.
(2) Description of the Related Art
Oxide spacers have been used to advantage in several different ways in the manufacture of semiconductor devices. They are used for structural as well as electrical and programmability reasons. A well-known structural use, shown in FIGS. 1a-1f, is in the manufacture of field effect transistors (FETs), which are also very well-known for their very small size, high packing density in the Ultra Scale Integration (ULSI) technology. Employing conventional methods, gate-oxide layer (30) is first formed over substrate (10) having already defined active regions bounded by passive field oxide regions (20) shown in FIG. 1a. A polysilicon layer is blanket deposited over the substrate and etched to form poly-gate (40), as shown in FIG. 1b. Gate-oxide other than that underlying the poly-gate is also etched away. Using poly-gate as a self-aligned mask, ion implantation is usually employed to form source and drain regions (15). Subsequently, an oxide layer (not shown) is formed over the substrate and anisotropically etched, following conventional methods, to form oxide spacers (50) shown in FIG. 1c. 
One of the early structural uses of oxide spacers such as shown (50) in FIG. 1d was in forming self-aligned silicide (SAC) contacts, which are well-known in the art. Thus, after the forming of the spacers, metal used to form the silicide is deposited over the substrate. The substrate is then heated, which causes the silicide reaction to occur wherever the metal is in contact with the silicon. Everywhere else, the metal remains unreacted. The unreacted metal is selectively removed through the use of an etchant that does not attack the silicide, the silicon, or the oxide. As a result, each exposed source and drain region is now completely covered by silicide film (60), but there is no film elsewhere. A dielectric layer, (70), is next deposited onto the silicide, and contact holes are opened in it down to the silicide layer following conventional techniques (FIG. 1e). Metal (80) is deposited into the contact holes to make contact with the silicide, which provides excellent electrical characteristics. Thus, oxide spacers perform the structural function of separating silicided areas from shorting each other.
However, spacers (50) on the sidewall of gates, hence sometimes called sidewall spacers, also provide an important function in aligning ion implants which in turn control electron flow to and fro between the floating gate and the channel in the semiconductor substrate. At the same time, when sidewall spacers are used to decrease cell size in a split gate flash by way of being formed of polysilicon so that they can function as a word line, they will in fact short with the substrate, especially when silicided for better electrical performance, unless they are shaped properly, as disclosed later in the embodiments of the present invention.
In prior art, U.S. Pat. No. 6,228,695 by Hsieh, et al., discloses a split-gate with self-aligned source and self-aligned floating gate formed as a spacer. That is, a poly-1 layer is first formed as a vertical control gate. Then, a poly-2 layer is formed as a spacer floating gate adjacent to the control gate with an intervening intergate oxide layer. The resulting self-aligned source alleviates punch-through from source to control gate while the self-aligned floating gate with respect to the control gate provides improved programmability. In another U.S. Pat. No. 6,204,126, Hsieh, et al., disclose a multi-self-aligned split-gate flash memory cell where the floating gate of the cell is self-aligned to trench isolation, to source and to word line. This multi-self-aligned structure provides the maximum shrinkage of a memory cell that is possible.
A dual-bit multi-level ballistic flash memory cell is shown in another U.S. Pat. No. 6,133,098 by Ogura, et al. Here, two side wall spacer floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Odanaka, et al., on the other hand, in U.S. Pat. No. 6,051,860 take advantage of a step provided by a spacer where a first surface region at a first level is formed, then a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together formed so that a channel with a triple structures formed. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof, thereby improving the efficiency with which the electrons are injected into a floating gate.
In order to enhance the function of spacers, however, and in some cases to prevent, it is important to form spacers of a certain shape as disclosed below.
Prior art shows the use of sidewall spacers for various purposes. It is shown in the present invention that by a judicious choice of a particular shape, the function of spacers can be enhanced further, and in some cases, unwanted shorts between the substrate and the controlling gates can be prevented.
It is therefore an object of the present invention to provide a method of forming a square spacer in a flash memory cell in order to prevent bridging between a word line and the substrate.
It is another object of the present invention to provide a method of forming a square spacer through using chemical mechanical polishing followed by etch back, instead of just etch back which yields non-square spacer which is susceptible to bridging with salicided word lines.
It is yet another object of the present invention to provide a split gate flash memory cell with a square poly spacer absent of any bridging between the substrate and salicided word line.
These objects are accomplished by providing a substrate having a plurality of active and field regions defined; forming a first oxide layer over said substrate; forming a first polysilicon layer over said first oxide layer; forming a first nitride layer over said first polysilicon layer; defining said first nitride layer to form a shallow trench isolation in said substrate; forming a self-aligned diffusion layer in said substrate; forming a second nitride layer over said substrate; patterning said second nitride layer to define a cell area in said substrate; etching through said patterning in said second nitride layer to form a sloped profile in said first polysilicon layer; forming a second oxide layer over said substrate, including over said sloped profile in said first polysilicon layer; planarizing said second oxide layer over said substrate; patterning said second oxide layer to form an opening including over said cell area; etching through said patterning in said second oxide layer to remove said second nitride layer over said cell area; etching further through said patterning in said second oxide layer to remove underlying said first polysilicon layer to form an opening until said substrate is reached; forming a third oxide layer over said substrate, including over said opening reaching said substrate; etching said third oxide layer to form an oxide spacer along the vertical walls of said opening reaching said substrate; forming a second polysilicon layer over said substrate, including over said oxide spacer in said opening reaching said substrate; planarizing said second polysilicon layer over said substrate; oxidizing said second polysilicon layer in said opening reaching said substrate to form a fourth oxide layer; removing said second nitride layer, thus exposing portions of said first polysilicon layer; removing said portions of said first polysilicon layer, thus exposing portions of said first oxide layer; removing said portions of said first oxide layer; forming a fifth oxide layer over said substrate, including over said fourth oxide layer and second oxide layer; forming a third polysilicon layer over said substrate, including over said fourth oxide layer; planarizing said third polysilicon layer until stopped on said fifth oxide layer over said cell area to form a flat top of said third polysilicon layer; etching back said third polysilicon layer to form a square polysilicon (poly)spacer; forming a third nitride layer over said substrate, including over said square poly-spacer; etching said third nitride layer to form a nitride spacer along the vertical walls, including that of said square poly-spacer; and forming salicide over said substrate, including over the top of said square poly-spacer to form a word line without any bridging between said word line and said substrate.
The objects of the instant invention are further accomplished by providing a split-gate flash memory cell having a square poly-spacer, which serves as a control gate coupled to a wordline. The cell comprises: a substrate; a gate oxide layer over said substrate; two floating gates sharing a source line therebetween said floating gates, wherein said floating gates are separated from said source line with an intervening oxide spacer; two oxide caps formed over said two floating gates; an oxide cap over said source line therebetween said floating gates; an intergate oxide layer encompassing said two floating gates and their said two oxide caps, including said source line with its own oxide cap therebetween; a square poly-spacer vertically adjacent said intergate oxide layer encompassing said two floating gates and source line therebetween; a salicide word line formed over the top of said square poly-spacer; and a nitride spacer formed on the vertical walls of said square poly-spacer and another nitride spacer adjacent said intergate oxide layer on the vertical walls of said floating gates.